1. Field of the Invention
The invention relates to testing of electronic circuits and in particular relates to improved methods and structures for timing delay fault (“TDF”) testing at high-speed using an on-chip phase lock loop (“PLL”).
2. Discussion of Related Art
Designers and manufacturers of integrated circuits test the fabricated circuits to verify proper design and fabrication. In earlier days of integrated circuit fabrication and design, so called “stuck at” signal testing often sufficed where tests could be performed by an external, automated test system to determine if a particular pin or signal, externally accessible from the integrated circuit, was stuck at a particular logic level rather than responding normally to the desired behavior of the integrated circuit. Such simple stuck at testing generally proceeded by applying an external stimulus to one or more input signal pins of the integrated circuit and verifying proper, expected output signals generated by the integrated circuit under test. The automated test system would generate and apply such external stimuli and would sense the proper response on associated output signal paths of the integrated circuit under test.
As design and fabrication techniques grew more complex and demands for quality increased, more sophisticated testing techniques have evolved. One such testing technique is often referred to as timing delay fault testing or “TDF” testing. In general, timing delay fault testing generates a rapid succession of clock pulses to verify a proper operation of aspects of an integrated circuit under test in response to the sequence of rapid test pulses. A first test pulse in TDF testing is referred to as the “launch clock” or “launch pulse”. A second successive generated clock pulse generated is referred to as the “capture clock” or “capture pulse”. In general, the TDF testing launch pulse initiates operation of a particular sequence of intended logic within the integrated circuit under test and the capture pulse verifies the state of the integrated circuit at a prescribed time delay after the launch pulse. Integrated circuit designs have rapidly increased in speed such that they utilize high frequency clock rates. TDF testing techniques and signals are generally operable at similar frequencies to the frequency at which the integrated circuit operates.
Automated test systems are highly complex and costly systems. Since integrated circuit clock rates have advanced rapidly, a problem has arisen in performing TDF testing using older, legacy automated test systems. The older, legacy automated test systems may be incapable of generating launch and capture clock pulses for TDF testing at a high enough frequency to adequately test present day integrated circuit designs and fabrication techniques. One solution, of course, is to discard and/or upgrade the older, legacy automated test system with more modern, higher speed test systems to permit TDF testing at higher clock frequencies. Such a solution may be impractical due to the significant capital cost associated with such automated test systems.
It is evident from the above discussion that a need exists for improved methods and structures to permit high speed TDF testing of integrated circuits without requiring costly upgrade of older legacy automated test systems.